1. Field of Invention
This present invention relates to digital control of three-phase power converters. Specifically, the present invention relates to digital control of three-phase boost power-factor-corrected (PFC) rectifier.
2. Discussion of the Related Art
The six-step, three-phase boost PFC rectifier is widely used in high-power AC-to-DC conversions. Such a PFC rectifier achieves both low total harmonic distortion (THD) in its currents and unity power factor. The six-step operation is based on dividing a line cycle into six segments, with each segment being one of six switch states generated from either line or phase input voltages. In each segment, a specific pair of switches (i.e., two switches affiliated with two corresponding enabled phase voltages) are controlled by pulse width modulation (PWM) to implement single-switch, single-phase boost PFC rectification for each of the two phase voltages. At any given time, a switch state signal determines which pair of switches is modulated. The switch state signal is generated by a decoder which decodes binary signals derived from the input voltages. Thus, the three-phase boost PFC rectifier operates as two parallel single-phase boost PFC rectifiers. The currents in these two enabled phase voltages can be shaped according to the switch state signal, while the output voltage is maintained at a desired level. The current in the third phase voltage (i.e., the disabled phase voltage) is not directly controlled, but it is determined by the currents in the other two enabled phase voltages.
One problem associated with the six-step PFC rectifier relates to segment identification for both balanced and unbalanced input voltages. For balanced input voltages, two techniques for segment identification are used in the industry. One technique, which is described in U.S. Pat. No. 5,329,439, entitled “Zero-Voltage-Switched Three Phase Pulse Width Modulating Switching Rectifier with Power Factor Correction,” to Dusan Borojevic, Fred C. Lee, and Vlatko Vlatkovic, detects zero-crossings of the three-phase voltages. In a balanced three-phase power system, the phase angle between any two phase voltages is 120°, and segment transitions occur at the phase voltage zero-crossing times. By decoding the zero-crossing signals of the input phase voltages, which are represented at logic high levels during the positive half-line cycle (i.e., 180°) and at logic low levels during the negative half-line cycle (i.e., 180°), six 60° segments may be obtained. However, this technique requires a neutral line, which may not be available in many practical applications. As a result, while this zero-crossing detection technique is applicable to a three-phase rectifier with a four-wire connection (e.g. a Wayne connection), it is not applicable to a three-phase rectifier with only a three-wire connection (e.g. a Delta connection).
Because most conventional three-phase rectifiers are used in three-wire systems (i.e., systems in which the neutral line is not available and in which phase-voltages are not accessible), a second segment identification technique detects line-voltage zero-crossing signals. Generally, the zero-crossing signals (ZRS, ZST, and ZTR) associated with the three unbalanced input-line voltages (VRS, VST, and VTR) cannot be directly used for segment identification. For balanced three-phase input voltages, however, phase-voltage zero-crossing signals can be indirectly derived from the known line-voltage zero-crossing signals by 30° phase shifting, using the fact that the phase shift between a line voltage and a corresponding phase voltage in a balanced system is 30° (e.g., the phase shift between line voltage VST and phase voltage VS is 30°). This technique, however, leads to rather complex implementations, because detecting the line frequency and its variations require a phase-locked loop (PLL) circuit. Furthermore, this technique is generally not applicable to unbalanced input voltages, for which the phase angle between line and phase voltages is not necessarily 30°. Because a six-step, three-phase converter which properly identifies segments in both balanced and unbalanced input voltages is especially important to current-shaping and output voltage regulation, a simple and robust segment signal identification scheme is desired.
A decoder which properly identifies segments may be implemented in either hardware or software. A basic decoder, which is typically employed in a conventional six-step, three-phase converter, uses combinational logic to convert its binary input signals (e.g., zero-crossing signals of the input voltages) into one of the six output codes. However, because the output codes of this basic decoder are determined using only its contemporaneous input signals, the basic decoder essentially operates open-loop. Since the binary input signals are usually obtained by voltage comparators from input voltages that are susceptible to disturbance, the decoder may generate a false switching state as its output. A false switching state increases switching losses, component stresses and distortions of line current waveforms. The effect of disturbance on the binary input signals may be reduced when a hysteresis band is incorporated into the voltage comparators that sense zero-crossings of input voltages. However, it is difficult to design an optimal hysteresis band, because the amplitude of an unexpected input-voltage disturbance is almost impossible to estimate. Moreover, an excessive hysteresis band may cause an unacceptable phase delay, which causes the line currents to be significantly out of phase with the corresponding input voltages. Therefore, a robust segment-signal decoder in a six-step, three-phase converter with disturbance rejection is desired.
Yet another problem relates to current glitches during segment transitions. Such glitches result from one phase abruptly changing its switching state from “disabled” to “enabled” (i.e., from an uncontrollable phase current state to a controllable phase current state), while another phase changes its switching state from enabled to disabled. During these switching state changes, the corresponding duty cycles must change from one local steady state value to another local steady state value under current loop regulation. However, due to the current loop's limited bandwidth, the duty cycle changes may not be fast enough, thereby creating current transients that are seen as current glitches in the line current waveforms at the instants of segment transitions. To reduce these current glitches, the disabled phase current feedback path may be suspended by keeping the integrator output of the current-loop controller at the same value as before it is disabled. This technique is described in the article, entitled “A Three-Phase ZVT Boost Rectifier with Improved Analog Controller” by Richard Zhang, Silva Hiti, Fred C. Lee, and Dusan Boroyevic, and published in the IEEE Power Electronics Specialists' Conference (PESC) Record, pp 469-474, 1996. However, the implementation described in the article requires two extra analog electronic switches and a synchronization signal for each of the three current loops, adding extra complexity to an already complex analog controller circuit. Thus, a simpler and more robust solution than that described in the Zhang article is desired.